Startup Introduces 7-Bit Flash Storage Per Cell With 10-Year Retention

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One of the main drivers of increasing the capacity of next-generation storage has been to increase the number of bits that can be stored per cell. The easy jump from one to two bits per cell gives a direct increase of 100%, in exchange for more control needed to read / write the bit, but also limits the endurance of the cell. We’ve seen the commercialization of up to four bits per cell storage, and we’re talking about five. A Japanese company is now ready to start talking about its new 7-bit per cell solution.


Image courtesy of Plextor, up to 4 bits per cell

Going from one to two bits per cell easily doubles the capacity, and going to three bits per cell is only an additional 50% increase. As more bits are added, the value of adding those bits decreases, but the cost of the equipment to control read and write increases exponentially. There must be an average balance between the number of bits per cell which makes economic sense and the cost of the control electronics to be implemented to activate these bits.

  • 1 bit per cell requires detection of 2 voltage levels, basic capacity
  • 2 bits per cell requires detection of 4 voltage levels, + 100% capacity
  • 3 bits per cell requires detection of 8 voltage levels, + 50% capacity
  • 4 bits per cell requires detection of 16 voltage levels, + 33% capacity
  • 5 bits per cell require detection of 32 voltage levels, + 25% capacity
  • 6 bits per cell requires detection of 64 voltage levels, + 20% capacity
  • 7 bits per cell require detection of 128 voltage levels, + 16.7% capacity

Also, the more bits per cell, the lower the endurance – the voltage variation when you store many bits only has to drift slightly to get the bad result, and therefore repeated reads / writes on a high capacity cell will derive this voltage. until the cell is unusable. Right now the market seems satisfied with three bits per cell (3 bpc) for performance and four bits per cell (4 bpc) for capacity, with a few designs at 2 bpc for longer term endurance. Some of the major vendors have worked on 5bpc storage, although the low endurance may make the technology only good for WORM – write once, read many, which is a common acronym for the equivalent of something like a CD to the old or not. DVD rewritable.

Floadia Corp., a Japanese C-series startup, issued a press release this week saying it has developed storage technology capable of seven bits per cell (7 bpc). Still in the prototype stage, this 7bpc flash chip, presumably in a WORM scenario, has an effective shelf life of 10 years for data at 150C. The company claims that a standard modern memory cell with this level of control would only be able to retail data for about 100 seconds. The secret of the design therefore lies in a new type of flash cell that they have developed.

The SONOS cell uses a distributed charge trap design based on a Silicon-Oxide-Nitride-Oxide-Silicon arrangement, and the company points to an effective silicon nitride film in the middle where charges are trapped to allow high retention. In simple voltage programming and clearing cycles, the company exhibits over 100,000 cycles with very low voltage drift. The oxide-nitride-oxide layers are based on SiO2 and Si3N4, the latter known to be easy to manufacture. This allows a non-volatile SONOS cell to be used in NV-SRAM or on-board designs, such as microcontrollers.

It’s actually this last point that means we’re a long way from seeing this in modern NAND flash. Floadia is currently partnering with companies like Toshiba to implement the SONOS cell in a variety of microcontrollers, rather than large NAND flash deployments, at the 40nm process node as an integrated flash IP with in-memory compute properties. . These are not yet at 7 bits per cell, with the effect that the company is promoting that two cells can store up to 8 bits of network weight for machine learning inference – when we come to 8 bits per cell, then it could be more applicable. The 10-year retention of cellular data is where it gets interesting, as the integrated platforms will use algorithms with fixed weights for the life of the product, with the possible exception of the rare update. . Even with increased longevity, Floadia doesn’t go into details regarding cyclability at 7bpc yet.

An increase in modern NAND flash from 3bpc to 6bpc would allow a double increase in density, but larger cells would be required which would negate the benefits. There is also the performance aspect if the development of> 4bpc ever reaches consumers, which has not been addressed.

It will be an interesting technology to follow.

Source: Flodia press release

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